High level synthesis (HLS) technology is often employed in the design and verification of integrated circuits (ICs) such as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), other programmable devices, and/or the like. For example, HLS technology may significantly reduce the time and effort involved in designing and verifying complex circuits.
As one example, HLS technology may be employed to transform a relatively abstract description of a circuit into a less abstract description of the circuit. For example, the relatively abstract description of the circuit may be a behavioral design description. However, HLS technology may also be employed for relatively abstract descriptions specified in other types of hardware description languages such as system-level modeling languages, and the like. In addition, HLS technology may generate the less abstract description of the circuit in any suitable description language. For example, the less abstract description of the circuit may include a register-transfer level (RTL) description, gate level description of the circuit, and/or the like.
In certain designs/circuits, clock signals to certain portions of the circuit may be selectively provided, selectively enabled, or otherwise gated. Such clock gating may affect circuit power consumption, e.g., by affecting the amount of circuitry that is clocked at particular times.